1. Technical Field of the Invention
The present invention relates to accessing a ferroelectric memory device, and particularly to a circuit and method for asynchronously accessing a ferroelectric memory device.
2. Description of the Related Art
Ferroelectricity is a phenomenon which can be observed in a relatively small class of dielectrics called ferroelectric materials. In a normal dielectric, upon the application of an electric field, positive and negative charges will be displaced from their original positionxe2x80x94a concept which is characterized by the dipole moment or polarization. This polarization or displacement will vanish, however, when the electric field returns back to zero. In a ferroelectric material, on the other hand, there is a spontaneous polarizationxe2x80x94a displacement which is inherent to the crystal structure of the material and does not disappear in the absence of the electric field. In addition, the direction of this polarization can be reversed or reoriented by applying an appropriate electric field.
These characteristics result in ferroelectric capacitors, formed from ferroelectric film or material disposed between parallel conduction plates, being capable of storing in a nonvolatile manner a first charge corresponding to a first polarization state in which the direction of polarization is in a first direction, and a second charge corresponding to a second polarization state in which the direction of polarization is in a second direction opposite the first direction. Ferroelectric capacitors are utilized in nonvolatile random access memory devices having a memory cell array architecture that is similar to the memory cell array architecture of dynamic random access memory (DRAM) devices.
In general terms, there are two types of ferroelectric memory cells. Referring to FIG. 1A, a one transistor, one capacitor (1T1C) memory cell utilizes a pass gate transistor T connected between a column line B and a first plate of ferroelectric capacitor C. A second plate of ferroelectric capacitor C is connected to a plate line P. The gate terminal of pass gate transistor T is connected to a word line W. A memory device utilizing a 1T1C memory cell uses a reference memory cell that is accessed at the same time the 1T1C memory cell is accessed so as to provide a charge differential appearing across a pair of column lines coupled to the 1T1C cell and the reference cell. The use of 1T1C ferroelectric memory cells is known in the art.
Referring to FIG. 1B, a two transistor, two capacitor (2T2C) memory cell includes two ferroelectric capacitors C1 and C2. A first pass gate transistor T1 is connected between a first plate of ferroelectric capacitor C1 and a first column line BL of a column line pair. A second pass gate transistor T2 is connected between a first plate of ferroelectric capacitor C2 and a second column line BLxe2x80x2 of the column line pair. A second plate of ferroelectric capacitors C1 and C2 is connected to a plate line P. The gate terminal of pass gate transistors T1 and T2 is connected to the word line W. Each capacitor C1 and C2 stores a charge representative of the polarization state thereof, the charge combining with the charge of the other capacitor to result in a charge differential appearing across column lines BL and BLxe2x80x2 when the 2T2C memory cell is accessed. The polarity of the charge differential denotes the binary value stored by the 2T2C memory cell. The use of 2T2C ferroelectric memory cells is known in the art.
Because ferroelectric random access memory (FRAM) devices are non-volatile, existing FRAM devices have been used to replace static random access memory (SRAM) devices, such as SRAM devices in low power applications. One complication in replacing SRAM devices is in reconciling the asynchronous operation of some SRAM devices with the synchronous operation of existing FRAM devices. In particular, because ferroelectric memory cells are destructively read, it is necessary to restore the data in the addressed memory cells during a memory read operation. Aborted memory read operations or address cycles being less than the minimum address cycle could corrupt data stored in the addressed memory cells. Consequently, memory access operations of FRAM devices are typically synchronous, in which addresses are sampled at the falling edge of the chip enable signal. In other words, the chip enable signal is used as a clock signal, such that each memory access operation requires the chip enable signal transition to the de-asserted state to latch the received address and transition to the asserted state to initiate a next memory access operation.
In contrast, conventional SRAM devices are asynchronous, in that memory access operations are executed without latching the address signals relative to a clock signal applied to the SRAM device. SRAM devices are capable of performing asynchronous memory access operations because memory read operations of an SRAM device are not destructive. Based upon the foregoing, there is a need to provide an FRAM device that is asynchronous and/or otherwise capable of effectively replacing asynchronous SRAM devices without unnecessarily limiting the operation of the system in which the SRAM device is disposed.
Embodiments of the present invention overcome shortcomings in existing FRAM devices and satisfy a significant need for an asynchronous FRAM device that is capable of effectively replacing an SRAM device. An embodiment of the present invention is an FRAM device that internally generates timing signals for latching a received address signal and driving the row lines of the FRAM device based upon transition s appearing on the received address signal. In particular, the FRAM device includes an address input buffer for receiving an address signal during a memory access operation, asserting an edge detect signal in response to at least one edge transition appearing on a bit of the address signal, and latching the address signal following the assertion of the edge detect signal. The FRAM device further includes address decode circuitry for receiving the latched address signal and generating decoded output signals identifying a row of memory cells to be accessed. By generating the edge detect signal in this manner and latching the address signal based upon the edge detect signal, the FRAM device behaves in a system a s an asynchronous FRAM device.
The FRAM device performs a memory access operation by asserting the edge detect signal in response to at least one edge transition appearing on the bit of the address signal; latching the address signal following the assertion of the edge detect signal; equilibrating and precharging column lines of the FRAM device and driving the row lines thereof to a low reference voltage level when the edge detect signal is asserted; receiving the latched address signal and generating decoded output signals identifying a row of memory cells to connect to the column lines based on the latched address signal; and coupling at least one selected column line to data input/output terminals of the ferroelectric memory device.